1. Field of the Invention
The present invention relates to a microprocessor capable of constructing a multi-microprocessor system having a plurality of microprocessors connected in series, and more particularly, to a microprocessor suitable for constructing a multi-microprocessor system in which a microprocessor receives reset information from the previous microprocessor, selects its own reset vector from a reset vector table and simultaneously generates its own processor ID and a reset ID to be transmitted to the next microprocessor.
2. Description of the Related Art
In a conventional multi-processor system, all of microprocessors of the system have the same reset vector. Accordingly, the multi-processor system must use a arbiter that makes the microprocessors of the system use a single reset vector to allow the microprocessors to be sequentially started up using an external complicated algorithm. Furthermore, when the multi-processor system uses a shared system bus, the respective microprocessors must have their own processor IDs in order to use the shared system bus. In this case, an additional arbiter is also needed to arbitrate the access of the microprocessors to the shared system bus.
U.S. Pat. No. 6,314,515 B1 applied by Compaq Computer Corporation and entitled “Resetting Multiple Processors in a Computer System” discloses a system using two processors P1 and PZ. In this system, a reset signal required for initializing the system is applied to the processor P1 to start up the processor P1 while the processor PZ is held using an inter-processor communication module such that the processor P1 ends a process required for initializing the system and then the processor PZ is started. That is, this system has an external inter-processor communication module for initializing more than two processors and holds one of the processors while the other processor is started up to secure initialization of the processors. However, this technique has shortcomings that initialization of the processors must be arbitrated using a complicated external arbiter circuit and algorithm and only one processor can be started at a time.
Japanese Patent No. 11-21068 applied by Doshiba Corporation and entitled “Reset vector switching method and information processor using the same” discloses a technique that receives a plurality of reset signals, generates a reset vector in response to the reset signals and changes an initialization address of a microprocessor in response to a reset signal input when the microprocessor is started. This technique requires a plurality of reset signals and prevents erroneous initialization of a program due to hardware failure in a single processor system. However, this technique must use an external arbiter similar to the arbiter of the aforementioned U.S. Patent to be applied to a multi-processor system.
Korean Patent No. 10-0201399 applied by LG Semiconductor Corporation and entitled “Reset interrupt circuit” discloses a system that receives port state inputs in addition to a reset signal and combines the port state inputs to select a new reset vector. This technique requires a plurality of port state inputs, selects a program in response to the state of external hardware and initializes the selected program in a single processor system. This system also needs an external arbiter similar to that of the aforementioned U.S. Patent system to be applied to a multi-processor system.